Typically, transmission gates are a source of noise and parasitics which directly produce error voltages in analog circuits. The most common source of error results from parasitic capacitance associated with transistors used to embody the transmission gate or switch. Parasitic capacitance charge couples an offset voltage to analog circuitry and exists primarily at the gate/drain and gate/source regions of transistors. A conventional CMOS analog switch utilizes a P-channel and an N-channel transistor which are clocked by complementary control signals. The two transistors are coupled in parallel. In an attempt to cancel the charge resulting from parasitic capacitance, others have used two capacitors with each having a first plate connected to an input and a second plate connected to a respective one of the two transistors. The capacitors utilize charge cancellation to limit an error voltage resulting from transients occuring during a transition of state of the control signals. However, since the capacitors cannot be perfectly matched, not all parasitic charge is effectively cancelled.
A second problem associated with transmission gates is the high "on" resistance which exists. A low resistance is desirable in order to allow coupling capacitors to quickly charge through the transmission gate. Previously, some transmission gates have utilized a "switched tub" gate as taught in U.S. Pat. No. 3,720,848 by Schmidt, Jr.. Although switching the tub or substrate of the N-channel transistor reduces the "on" resistance of the switch, the switching action may couple in electrical charge and produce an error voltage.